(a) Field of the Invention
The present invention relates to a flash memory device and a method of manufacturing the same. More particularly, the present invention relates to a flash memory device including protrusions and depressions on a floating gate, and a method of manufacturing the same.
(b) Description of the Related Art
Generally, a flash memory is devised to combine advantages of both EPROM (erasable programmable read only memory) and EEPROM (electrically erasable PROM), which provides a device enabling electrical data programming and erasing with a low manufacturing cost due to a simple manufacturing process and small chip size.
Flash memory is a non-volatile semiconductor memory in which data is not destroyed by breakage of a power supply, which also has a property of RAM (random access memory) meaning that programming and erasing of information can be easily performed electrically in a system. Due to the above characteristics, flash memory is used for a memory card, as a memory device substituting a hard disk of portable office automation instruments, and so on.
Data programming of a flash memory is performed by implantation of hot electrons. That is, when hot electrons are generated in a channel due to a potential difference between a source and a drain, some electrons that obtain energy of equal to or more than a potential barrier between a gate polysilicon and an oxide move to, and are stored in, a floating gate by a high electric field applied to a control gate.
Hereinafter, a conventional flash memory device will be briefly described with reference to FIG. 1 to FIG. 3.
FIG. 1 is a top plan view with respect to a single cell in a flash memory, and FIG. 2 and FIG. 3 are respectively cross-sectional views along lines II-II and III-III in FIG. 1.
As shown in FIG. 1 to FIG. 3, a gate oxide layer 20 is formed in a portion of a device region in a semiconductor substrate 100, and a floating gate 30 including polysilicon is formed on the gate oxide layer 20. Since the floating gate 30 is not connected to an outside, it performs a function of a storage node for electrons.
In addition, a dielectric layer 40 is formed on the floating gate 30. The dielectric layer 40 includes an ONO structure in which an oxide layer, a nitride layer, and an oxide layer are sequentially accumulated.
Subsequently, a control gate 50 including polysilicon is formed on the dielectric layer 40, and it performs a function of a gate at a general MOS transistor. In addition, a spacer (not shown) is formed on sidewalls of a gate including a gate oxide layer 20, floating gate 30, dielectric layer 40, and control gate 50, and then an LDD (Lightly doped drain) (not shown) is formed on the semiconductor substrate 100 below the spacer by ion-implanting low-concentration impurities having opposite conductivity to that of the semiconductor substrate 100. By ion-implanting high concentration impurities having the same conductivity as that of the LDD, a source region 70 and a drain region 80 are formed in the exposed portion of the semiconductor substrate 100 contacted with the LDD.
In addition, a contact 90 is formed in the drain region 80 such that it is electrically connected with an outside.
As shown in FIG. 1 to FIG. 3, the dielectric layer 40 insulates between the floating gate 30 and control gate 50, and high voltage may be required for performing a program operation by moving hot electrons from the control gate 50 to the floating gate 30 through the dielectric layer 40. However, since a transistor of a charging pump needs to have a larger size than a predetermined size in order to apply high voltage, chip size may be increased.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.